Design and Implementation of Ternary Logic Gates over a Quaternary Logic

Ternary logic is MVL compliant. However, only three logic states are used “0”, “1” and “2”. The optimum radix (r) of a fractional number is found to be the natural logarithm (e). Ternary logic uses number representation with r=3, compared to quaternary logic which uses r=4, hence the most economical integer radix which is the closest to the natural logarithm e, is base 3 [3]. This special property of base 3 inspired the early computer designers to build a ternary computer. According to the ITRS1 we will face the brick wall in 2015 if we continue in the same development speed. So we have to come up with other solutions, and MVL is one of most promising one. MVL can in principle increase data processing capability per unit chip area in the future. It is true that the noise margins are a serious issue, which is the reason why my solutions are ternary. This will keep the noise margins at an acceptable level. In 2004, a research team in Rennes made a MVL Chip using Supplementary Symmetrical. The application of MVL to asynchronous circuits can be an effective way to the design of low power high-performance VLSI digital circuits [6]. Index Terms – MVL, BT, RSFG, STI, NTI, PTI.